Session 3 · Exercises 1 and 2

HBM design calculator

Two reasons HBM has the shape it has today, checked with numbers. One is power. HBM builds its bandwidth from a great many slow pins rather than a few fast ones. The other is yield. The higher you stack dies, the more good dies get thrown away along with the bad.

① Wide and slow, or narrow and fast

B = bus width × per-pin data rate　·　power = (B × 8) × pJ/bit × number of stacks

Product presets

Target bandwidth per stack

Stacks per accelerator

(a) Narrow and fast

Required per-pin data rate

pJ/bit

One stack
One accelerator

(b) Wide and slow

Required per-pin data rate

pJ/bit

One stack
One accelerator

The starting pJ/bit values come from the rough sense of scale that Exercise 2 in the text gives for 4 TB/s. For (a) it is 3, the value the solution uses in its worked calculation (the low end of the 3–5 range); for (b) it is the middle of the 0.5–1 range. Changing the target bandwidth changes the pin speed, so you have to move pJ/bit yourself. This page does not turn the relation between pin speed and pJ/bit into a formula. The text has no such formula, and real values differ by circuit and process.

The product presets set the target bandwidth per stack from the Section 4 table of specifications by generation, the list below it, and route ① in Section 3. Bandwidth is computed as pin speed times interface width. The standard column is what the pin speed set by the JEDEC standard can deliver; volume-production HBM4 has gone past the standard pin speed. The HBM4E sample press release does not state the interface width, so, as in the text, it is taken as 2,048 bits, the same as HBM4. GDDR7 is a value for one device, not a stack (JESD239, up to 192 GB/s per device), so it leaves the target bandwidth unchanged. SPHBM4 (JESD330-4), which mixes the two routes, uses the same DRAM die as HBM4 but cuts the data signals from 2,048 to 512 and reaches the same total bandwidth through 4:1 serialization. With fewer pins it can sit on an ordinary organic substrate instead of a silicon interposer. The press release does not say what that costs in pJ/bit, so it is left out of this figure.

② The higher the stack, the more good dies go out with the bad

Y_stack = yⁿ × y_bondⁿ⁻¹　·　good dies discarded = n·y − n·Y_stack (expected value per stack)

Die yield y

Stack height n

Bond yield y_bond

Screening before stacking (KGD)

Stack yield
Good dies in one failed stack
Completed per 1,000 stacks
Good dies discarded
Share of good dies wasted

Good die Bad die Good die discarded with a failed stack Red border = failed stack

Check against the solution tables ()

Values from the Session 3, Section 5 numerical examples and the solution tables for Exercises 1 and 2, recomputed with the formulas of this figure. Solution values are rounded. "Rounding diff" marks cases where the solution multiplied rounded intermediate values (e.g. 0.961 × 0.985) and so differs from the exact value in the last digit.
Item	Computed	Solution

What this calculation leaves out

The pJ/bit figures are a range the text explicitly qualifies as "a rough sense of scale". They are not vendor measurements.
The yield formula treats die defects as independent. Real defects tend to cluster on the wafer.
"Perfect screening" is the extreme case in which KGD testing misses no defect at all. The cost of the test itself and its miss rate are not included.
The effect of repairing defects with redundancy circuits is assumed to be already included in the die yield y.
Actual pin speeds and stack bandwidths for each HBM generation vary by vendor and product. In the Section 4 generation table of the text, the HBM2E and HBM3 values and the HBM3E row are rough ranges; HBM4 and HBM4E are manufacturer announcements.