Three of the heat-and-distance problems of Session 6, checked in numbers: the chain of thermal resistances out of the package, the energy per bit set by wire length, and the temperature difference between layers when chips are stacked. Thermal resistances add in series.
① Heat leaving the package — a series chain
Tj = Ta + P · (θJC + θTIM + θSA) · per-stage ΔT = P × θ
Ambient temperature TaθSA heat sink–ambientθTIMθJC junction–case
Sum of θ
ΔT junction–case
ΔT TIM
ΔT heat sink–ambient
Total ΔT
Junction temperature Tj
vs. Tj,max
In a package with a heat sink, heat flows in turn from junction → case → TIM → heat sink (or cold plate) → ambient (air or coolant). The path is in series, so the resistances add. All starting values are the assumed values of the worked example in Section 7 of the text, not values of any particular product. Ta can also be read as the coolant inlet temperature. The assumed values give the TIM the largest share in order to preview the point of Session 7, Section 3: the thin layer between chip and cold plate easily becomes the bottleneck of the whole chain. Tj must stay below the maximum junction temperature Tj,max set by each product's datasheet. The text gives no such number, so the field is left empty.
Check against the worked example in the text ()
The worked example of Session 6, Section 7, "Viewing it as a series chain" (P = 1,000 W, Ta = 35 °C, θ 0.015, 0.025, 0.020 K/W), recomputed with this figure's formulas.
Item
Computed
Text
② Wire length and energy per bit
C ∝ length → E = ½CV² (same V), so energy ratio = length ratio · power = pJ/bit × bit/s
Bit rate
Length ratio = energy ratio
TSV side
Substrate side
Bit rate
Power · TSV
Power · substrate wiring
Difference
If parasitic capacitance is taken as proportional to length, then by E = ½CV² at the same voltage the energy per bit differs by the length ratio too. The TSV-side 0.05 pJ/bit is the value set in the solution to Exercise 2. With one HBM stack at 4 TB/s = 3.2 × 10¹³ bit/s, eight stacks come to 12.8 W against 2,560 W. A single package draws power on the kilowatt scale, and this would spend 2.56 kW on memory wiring alone, so under this assumption the design does not work. If the distance cannot shrink, that bandwidth cannot be delivered within the power budget. Bandwidth → power → distance → packaging form one chain.
Check against the solutions ()
The table in Session 6, solution to Exercise 2 (10 mm vs. 50 μm, TSV 0.05 pJ/bit), and values in the text, recomputed with this figure's formulas.
Item
Computed
Solution
③ Temperature difference between stacked layers — silicon and interfaces
R = t / (kA), A = 1 mm² · ΔT of segment j = (j × power per layer) × (RSi + Rinterface), j = 1 … number of layers
Interface thermal resistance
ΔT across siliconΔT across interfaces (bumps, underfill, adhesive)
Heat flux per footprint
Silicon R (1 mm²)
Interface R (1 mm²)
Silicon total
Interface total
Interface ÷ silicon
Per 1 mm², with heat leaving only upward and every layer dissipating at the same power density (the assumption of the solution to Exercise 4). Heat from a lower layer must pass through every layer above it, so higher segments carry more heat. Silicon conducts heat very well: silicon alone gives only 3.3 K across 4 layers. The microbumps, underfill and adhesive between layers have an effective thermal conductivity of about 1–5 W/(m·K), around 1/50 of silicon, and these bonded interfaces are the bottleneck. There are as many interfaces as layers: one between each pair of layers, plus one joint between the top die and the heat-removal surface, all of the same material (four for 4 layers). "Excluded" is an idealization that sets the thermal resistance of every interface, up to the top joint, to zero. Hybrid bonding still leaves copper and dielectric bond faces, so this does not stand for the effect of an actual process change.
Check against the solutions ()
The table in Session 6, solution to Exercise 4 (1 W/mm², silicon 50 μm at 150 W/(m·K), interface 20 μm at 3 W/(m·K)), and values in the text, recomputed with this figure's formulas.
Item
Computed
Solution
What this calculation leaves out
Datasheet θJA, θJC and θJB are the difference between the junction temperature Tj and a reference-point temperature, divided by power P (JEDEC JESD51 series). θJA is measured on a standard test board in still air or at a set airflow, so it changes when the board or the airflow changes. ψJT and ψJB, used to back out Tj on a real board, have the same form as θ but are characterization parameters, not true thermal resistances. This page computes only the series chain of ①.
Higher temperature raises leakage current, and more leakage produces more heat: a positive feedback (Section 7). Here P and the power per layer are fixed values independent of temperature. The text gives no formula for that feedback.
The multiples in ② assume equal capacitance per unit length and equal voltage. Real wires differ in cross-section, insulator, parasitics and driver circuits, so this ratio does not come out as is. Substrate I/O often uses a larger voltage swing for signal integrity, which can widen the gap through the V² term. The text gives no voltage values, so voltage is not adjustable.
③ follows the assumptions of the solution to Exercise 4 as they are: per 1 mm², heat leaving only upward, the same power density in every layer. The starting interface effective thermal conductivity of 3 W/(m·K) is the value the solution picked from the range of about 1–5 given in the text.